1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof and, more particularly, to a semiconductor device having a plurality of interconnection layers with different widths and a manufacturing method thereof.
2. Description of the Related Art
To form a line-and-space interconnection pattern on a semiconductor substrate, for example, a method is known in which an interconnection pattern is buried in trenches formed in an insulating layer, thereby forming lines and spaces. In this method, a mask having the same pattern as a line-and-space interconnection pattern that is resolvable by an exposure technique is formed. Using this mask, an underlying layer formed from an insulating layer is patterned to form trenches. An interconnection material is buried in the trenches of the processed underlying layer. Then, the unnecessary interconnection material is removed by, e.g., chemical mechanical polishing (CMP), thereby obtaining a desired interconnection pattern.
In manufacturing a memory or the like, interconnections having a large width are sometimes formed in lines and spaces of the same pitch. To form narrow interconnections and wide interconnections in different lithography processes, it is necessary to ensure a large space between a narrow interconnection and a wide interconnection in consideration of the alignment margin. This makes it difficult to microfabricate a semiconductor device.
An associated technique of this type is also disclosed, which manufactures an LSI having a more sophisticated function by projecting and exposing an LSI pattern including a plurality of functional blocks onto a substrate via a lens using an optimum exposure method conforming to the characteristics of a pattern in a selected region (Jpn. Pat. Appln. KOKAI Publication No. 6-181164).